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The present invention relates to a memory controller for a double data rate synchronous dynamic random access memory (DDR SDRAM) device and, more particularly, to a memory controller configured to handle data transfers which exceed the page width for a DDR SDRAM device.
In recent years, the use of DDR SDRAM devices in memory subsystems has become increasingly common. While DDR SDRAM devices are commercially available in a wide variety of configurations, one currently available DDR SDRAM device has a 64 Mbitxc3x9716 memory chip configuration which provides a total memory of 8 Mbyte for a single chip. As the page size for such a device is 512 bytes, it is limited to one continuous burst of up to 512 bytes.
The newly developed advanced high performance bus (AHB) is configured to handle data transfer requests of up to 1,024 bytes. As a result, AHB devices which comply with the AHB protocol are capable of handling data transfer requests of 1,024 bytes for both incrementing and wrapping bursts. Because of the enhanced capabilities of AHB devices, when designing a memory controller for a DDR SDRAM, it is oftentimes necessary to require that the memory controller be configured to handle data transfer requests of up to 1,024 bytes. As DDR SDRAMs having a 64 Mbitxc3x9716 configuration are limited to continuous bursts of no more than 512 bytes, they are not suitable for use in memory subsystems intended to handle requests from AHB devices. As a result, the choice of memory chips available to the designer of an AHB-compliant memory subsystem has become unnecessarily limited.
For these reasons, it would be desirable to have a memory subsystem configured to reduce the effect of the configuration of the memory chip itself as a limit on the capability of the associated memory subsystem to handle data transfer requests.
In various embodiments thereof, the present invention is respectively directed to a memory controller, a memory subsystem and a computer system in which the memory controller includes first and second decoder circuits and a multiplexer circuit. The first decoder circuit generates a first input command for a data transfer request if the request relates to a data transfer sized at or below a threshold value while the second decoder circuit generates second and third input commands for a data transfer request if the request relate to a data transfer sized above the threshold value. The multiplexer circuit is configured to selectively pass the first input command generated by the first decoder circuit if the data transfer is sized at or below the threshold value or the second and third input commands generated by the second decoder circuit if the data transfer is sized above the threshold value. The threshold value may be determined from a page size for the memory, a size of the data transfer request and a starting address, within the memory, for the data transfer request.
In various aspects of these embodiments of the invention, the multiplexer circuit is further configured to include a pair of 2:1 multiplexers, each having first and second inputs and an output. The first and second inputs to the first multiplexer are coupled to the first and second decoder circuits, respectively. The first and second inputs to the second multiplexer, on the other hand, are coupled to the output of the first multiplexer and the second decoder circuit. In these aspects of the invention, if the data transfer request relates to a data transfer sized at or below the threshold value, the first multiplexer passes the first input command generated by the first decoder circuit and the second multiplexer passes the first input command passed by the first multiplexer. Further, if the data transfer request relates to a data transfer sized above the threshold value, the first multiplexer passes, in sequence, the first input command generated by the first decoder circuit and the third input command generated by the second decoder circuit and the second multiplexer passes, in sequence, the second input command generated by the second decoder circuit and the third input command generated by the second decoder circuit.